A TRUSTWORTHY CYCLIC REDUNDANCY–ORIENTED ERROR CONTROL SCHEME FOR FINITE FIELD MULTIPLIERS IN CRYPTOGRAPHIC ENGINES

Abstract

Finite-field multiplication plays a critical role in encryption and error-detecting codes, yet it remains a computationally intensive and hardware-expensive operation, often requiring millions of logic gates for modern cryptographic algorithms. This paper presents a case study of the Luov cryptographic algorithm and proposes a hardware architecture leveraging cyclic redundancy check (CRC) for error detection in post-quantum cryptography (PQC) applications. The selected CRC polynomials offer robust error-detection capabilities and are well-suited for the specified field widths. To validate the correctness of the proposed schemes, we develop verification algorithms that facilitate software-based testing. Hardware implementations of the original multipliers on a Xilinx field-programmable gate array (FPGA) confirm that the proposed error-detection techniques achieve effective error coverage with minimal overhead. The results highlight the practicality and reliability of integrating CRC-based error detection into PQC multiplier architectures.