DESIGN OF LOW-POWER VLSI ARCHITECTURE FOR HIGH-SPEED COMMUNICATION

Abstract

The rapid growth of high-speed communication systems has increased the demand for energy-efficient VLSI architectures capable of operating at high data rates. Power consumption has become a critical design constraint due to batteryoperated devices, thermal limitations, and reliability concerns in modern integrated circuits. This paper presents the design and analysis of a low-power VLSI architecture optimized for high-speed communication applications. Various power reduction techniques at architectural, circuit, and system levels are explored and integrated into the proposed design. The architecture focuses on minimizing dynamic and leakage power while maintaining high throughput and low latency. Simulation-based evaluation demonstrates that the proposed design achieves significant power savings without degrading performance. The results validate the effectiveness of the adopted low-power strategies. The proposed architecture is suitable for next-generation communication systems.