A REFINED AND EXPEDIENT THREE-OPERAND BINARY ADDER DEVISED BY MEANS OF REVERSIBLE LOGICAL ARTIFICE

Abstract

In the present age, wherein the reduction of power dissipation and the conservation of logical resources are esteemed of paramount consequence, reversible computation has emerged as a most promising discipline. The work proposes an efficient three-operand binary adder constructed upon reversible logical principles, thereby reducing information loss and the associated energy dissipation and found in conventional irreversible circuits. Unlike traditional adders which dissipate power through redundant transitions and discarded bits, the reversible scheme preserves a one-to-one correspondence between inputs and outputs, ensuring minimal logical waste. The devised architecture integrates carefully selected reversible gates so as to accomplish simultaneous addition of three binary operands with reduced ancillary outputs and moderated propagation delay. Particular attention has been given to reduction of power,area,delay,quantum cost, garbage outputs, and constant inputs, these being critical measures of merit in reversible design. The arrangement exhibits improved computational speed and enhanced energy effiency while maintaining structural regularity suitable large-scale integration. Thus, the proposed three-operand adder stands as a forward-looking contribution toward low-power arithmetic units suited for advanced digital and quantum-inspired systems.