AN ENERGY-CONSCIOUS AND HIGH-VELOCITY ADDER ARCHITECTURE EMPLOYING NOVEL XOR–XNOR LOGIC CONFIGURATIONS

Abstract

In this work, we propose hybrid 1-bit full-adder (FA) circuits leveraging recently developed XOR, XNOR, and XOR/XNOR gates. These designs optimize both power consumption and speed compared to conventional adder circuits, with low output capacitance enhancing their practical applicability. Each proposed adder demonstrates distinct advantages in terms of speed, power efficiency, and suitability for motor control applications. Simulations are performed using the TANNER tool with an 18-nm CMOS process, and results indicate superior performance relative to baseline designs. The study further examines circuit behavior under varying input voltages and output loads. Additionally, a novel class of circuits capable of performing XOR, XNOR, and XOR/XNOR operations simultaneously is introduced, exhibiting reduced short-circuit power dissipation and low output capacitance. To achieve optimal power-delay product (PDP), transistor sizing is refined using a numerical particle swarm optimization technique. Comprehensive analyses explore the effects of supply and threshold voltage variations, output capacitance, input noise immunity, and transistor sizing. Overall, the proposed circuits offer significant improvements in speed, power consumption, and PDP, making them highly effective for modern digital applications.