A SCHOLARLY EXAMINATION OF THE CONSTANCY AND LEAKAGE MODERATION IN A FULLY SELECTED ELEVENTRANSISTOR STATIC RANDOM-ACCESS MEMORY CELL

Abstract

This study presents two novel 11T SRAM cell architectures, 11T-1 and 11T-2, designed to be entirely half-select-free for efficient bit interleaving. Both architectures employ powercutoff mechanisms and write-‘0’/‘1’-only strategies to mitigate Read disturb and Write half-select disturb issues, while simultaneously enhancing write-ability. At a supply voltage of 0.9 V, the proposed cells achieve approximately twice the read and write yield of conventional 6T SRAM cells. The 11T-1 cell demonstrates a mean write margin (WM) 13.6% higher than existing 11T designs, and neither cell suffers from the floatingnode problem associated with previous powercutoff implementations. Monte Carlo simulations confirm robust low-voltage operation without auxiliary circuits. Furthermore, the study examines the impact of 32 nm high-k metal gate CMOS technology variations on SRAM reliability, particularly focusing on Bias Temperature Instability (BTI) and its effect on performance. The Read Static Noise Margin (RSNM) of all cells is observed to decrease under static stress, emphasizing the importance of stability considerations in advanced SRAM designs. The findings are validated across various digital arithmetic circuits including Ripple Carry Adders (RCA), Kogge-Stone Adders (KSA), and BrentKung Adders (BKA), highlighting improvements in transistor count, gate count, power consumption, and delay.